RIA’s AI in Semiconductor Design track is for engineers and analysts who work with fab, test, and EDA data. You learn how AI supports yield learning, virtual metrology, wafer inspection and layout copilots.
It does not replace Professional VLSI & Semiconductor Design (Verilog, UVM, FPGA, physical design). Use both if you want RTL plus AI-on-the-flow.
Domain literacy + applied AI labs + responsible review + capstone
We teach AI that sits on the semiconductor design and manufacturing flow — yield, lithography, metrology, EDA copilots and design-for-manufacturing — complementary to RIA’s RTL/UVM VLSI programme, not a replacement for it.
No. VLSI is RTL, verification and physical design. This track applies AI to yield, inspection, metrology and EDA assist on that flow.
Helpful, not mandatory. We teach process literacy first; practising process/yield engineers accelerate into modelling labs.
No. Labs use public or synthetic datasets. Real foundry work stays under NDA with human review.
Enquire with RIA for batch schedules, mentoring and project support at Purasawalkam or Saligramam, Chennai.