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AI-Enabled VLSI Design & Semiconductor Engineering

School of Technology & AI · Semiconductor & VLSI

Design intelligent silicon systems, from RTL to implementation

RIA’s AI-Enabled VLSI Design & Semiconductor Engineering programme is a project-based track through digital electronics, RTL development, verification, FPGA prototyping, ASIC implementation, low-power engineering and AI-assisted chip optimization.

Suggested duration is 6–8 months, with theory, labs and an implementation capstone. Batch dates, delivery format and the certificate issued for a cohort are confirmed when you enquire. It sits beside Professional VLSI & Semiconductor Design, AI in Semiconductor Design and Semiconductor & Photonics.

What you will learn

  • Semiconductor fundamentals and digital electronics
  • Verilog HDL, RTL design, verification and FPGA prototyping
  • ASIC synthesis, static timing analysis and physical design
  • Low-power VLSI and power, performance and area trade-offs
  • Machine learning on synthesis and timing reports
  • AI-assisted electronic design automation, with an engineer in the review
  • AI hardware accelerators and edge inference
  • Python, TCL and repeatable design-workflow automation

Full syllabus

12 modules · practical assignments · industry-oriented capstone

  • Module 1 — Semiconductor Fundamentals and Digital Electronics
    • Semiconductor materials, diodes and transistors
    • CMOS technology and logic gates
    • Number systems, Boolean algebra and logic minimization
    • Combinational and sequential circuits
    • Introduction to integrated-circuit design and semiconductor manufacturing

    Practical: Design and simulate fundamental digital logic circuits.

  • Module 2 — Verilog HDL and RTL Design
    • Verilog syntax, data types, operators and modules
    • Combinational and sequential RTL modelling
    • Multiplexers, decoders, counters and registers
    • Finite state machines
    • RTL coding standards and synthesizable design

    Practical: Build a controller, counter and sequence detector in Verilog.

  • Module 3 — Functional Verification and Testbench Development
    • Simulation and waveform analysis
    • Testbench architecture and stimulus generation
    • Assertions and functional coverage
    • Debugging RTL design failures
    • Design-for-test, scan testing and fault models

    Practical: Verify a FIFO or an FSM-based digital subsystem.

  • Module 4 — FPGA Design and Hardware Prototyping
    • FPGA architecture and the development workflow
    • RTL synthesis, pin constraints and implementation
    • Clocking, reset and timing constraints
    • Hardware debugging and on-board validation
    • FPGA and ASIC design considerations

    Practical: Implement a digital system on an FPGA board or a supported simulator.

  • Module 5 — ASIC Synthesis and Design Constraints
    • RTL synthesis and technology mapping
    • Standard-cell libraries and netlists
    • Timing constraints and SDC fundamentals
    • Area, power and performance metrics
    • Static timing analysis

    Practical: Synthesize an RTL block and evaluate area and timing reports.

  • Module 6 — Physical Design and RTL-to-GDSII
    • Floorplanning and power planning
    • Placement and congestion analysis
    • Clock tree synthesis
    • Routing and parasitic extraction
    • Design rule check, layout versus schematic and sign-off

    Practical: Run an available RTL-to-layout flow and interpret the implementation reports.

  • Module 7 — Low-Power VLSI Design and Optimization
    • Dynamic and leakage power
    • Clock gating and switching-activity reduction
    • Power-aware RTL design
    • Multi-threshold cells and power intent
    • Power, performance and area trade-offs

    Practical: Compare RTL alternatives for power, timing and area.

  • Module 8 — AI and Machine Learning for Semiconductor Design
    • Python for engineering data analysis
    • Regression, classification and model limits
    • Features from synthesis and timing reports
    • Predictive models for power, performance and area
    • Design-space exploration with optimization methods

    Practical: Build a model that predicts design metrics from experiment results.

  • Module 9 — AI-Assisted EDA and Intelligent Design Automation
    • AI-assisted RTL review and documentation
    • Assistant-supported testbench and test-case drafts, reviewed by an engineer
    • Automated reading of timing and synthesis reports
    • Models for timing, congestion and PPA prediction
    • Optimization loops, experiment tracking and result checks

    Practical: Build an assisted workflow that recommends RTL checks an engineer still accepts.

  • Module 10 — AI Hardware Accelerators and Edge Computing
    • Processor and accelerator architecture
    • Fixed-point arithmetic and numerical precision
    • Neural-network inference and hardware acceleration
    • Quantization and resource use
    • Hardware–software co-design and edge AI

    Practical: Design a small compute accelerator or an inference-oriented hardware prototype.

  • Module 11 — EDA Automation, Scripting and Engineering Workflows
    • Python and TCL for design automation
    • Batch runs and report extraction
    • Repeatable experiments and version control
    • Automated PPA comparison and regression checks
    • Responsible use of assistants, with an engineering review

    Practical: Automate a repeatable design evaluation and reporting pipeline.

  • Module 12 — Capstone, Portfolio and Career Preparation
    • Requirements and architecture specification
    • RTL implementation, verification and optimization
    • Synthesis, timing and physical-design evaluation
    • AI-based design analysis and a comparison report
    • Documentation, demonstration and project defence

    Practical: Deliver a documented semiconductor design project with repeatable results and a technical portfolio.

Capstone options

  • Intelligent RTL optimization. Compare RTL alternatives and use design reports to find power, performance and area improvements.
  • AI inference accelerator. Implement a simplified neural-network compute block with fixed-point arithmetic.
  • Timing prediction. Use design metrics and report data to estimate timing and flag likely violations.
  • FPGA signal processing. Build and check a digital signal-processing module on an FPGA or a simulation platform.

Tools and lab environment

Teaching uses the tools available in the RIA lab. Named commercial suites are examples of professional flows. A batch uses them only when that licence and lab access are in place.

AreaTools used in teaching
Hardware descriptionVerilog HDL, with SystemVerilog fundamentals
Simulation and verificationIcarus Verilog, Verilator, GTKWave
FPGAAMD Vivado, where the lab supports it
Synthesis and physical designYosys, OpenROAD, and a commercial flow only when licensed for the batch
AI and dataPython, NumPy, pandas, scikit-learn
AutomationPython, TCL, Git
Design metricsTiming, area and power reports, and PPA comparisons

Who this is for, and what you can do afterwards

Eligibility

  • BE, BTech, ME, MTech or MSc learners in ECE, EEE, electronics, instrumentation, VLSI, computer science or a related field
  • Early-career engineers moving into semiconductor design
  • Embedded and firmware engineers who want a hardware-design path
  • Software and AI learners specializing in hardware and design automation

A working start in digital electronics and programming is recommended. Learners who need it begin with the foundations in Module 1.

Learning outcomes

  • Develop and verify synthesizable RTL
  • Follow ASIC synthesis and physical implementation
  • Read timing, area and power reports
  • Apply basic low-power design methods
  • Build Python models for design analysis
  • Automate selected tasks with scripts and reviewed AI assistance
  • Present a documented VLSI or AI-hardware capstone

Common questions

  • How long is the programme?

    The planned length is 6–8 months. The cohort calendar, lab hours and certificate for a batch are confirmed when you enquire.

  • Which roles does this prepare for?

    Entry and developing roles in RTL design, digital verification, FPGA development, ASIC design, physical design, semiconductor automation and AI hardware engineering.

  • How is this different from the other semiconductor courses?

    Professional VLSI & Semiconductor Design follows the chip-design flow through verification and physical design. AI in Semiconductor Design applies AI to yield, inspection and EDA assist. This programme combines RTL-to-implementation practice with machine learning on design reports, assisted EDA and hardware accelerators.

Enquire about AI-Enabled VLSI

Explore related RIA technology programmes

VLSI & Semiconductor Design
AI in Semiconductor Design
Semiconductor & Photonics
School of Technology & AI

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The same formats sit on any RIA subject. Name the course and the room — a faculty programme, a seminar, a workshop, an internship, or help with a project.

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