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Professional VLSI & Semiconductor Design

School of Robotics

Don't just learn Verilog — learn how a semiconductor chip is designed

RIA's Professional VLSI & Semiconductor Design Program covers the complete semiconductor design flow — semiconductor fundamentals, digital logic, CMOS, Verilog/SystemVerilog, RTL design, UVM verification, FPGA, synthesis, STA, physical design, DFT, SoC and AI hardware.

Positioning: RTL • Verification • FPGA • ASIC • Physical Design • SoC • AI Hardware — Design | Verify | Synthesize | Implement | Test | Build. Part of RIA's Semiconductor & Intelligent Hardware pathway alongside PLC & Embedded Systems, EV Engineering, Drone Engineering and Medical Robotics.

What you will learn

  • Semiconductor physics, MOSFET/CMOS and digital logic through ALU and FSM design
  • Verilog and SystemVerilog RTL — UART, SPI, I2C, FIFO, CDC and IP blocks
  • Functional verification, assertions, coverage and UVM testbench environments
  • FPGA implementation on Xilinx/Intel/Lattice boards with Vivado/Quartus
  • Logic synthesis, static timing analysis, setup/hold and constraint-driven design
  • Physical design — floorplan, placement, CTS, routing and signoff (DRC/LVS)
  • DFT — scan chains, ATPG, JTAG, BIST and test architecture
  • SoC architecture, AMBA/AXI bus protocols and semiconductor IP integration
  • AI hardware accelerators — MAC arrays, NN inference RTL and AI-assisted EDA
  • Capstone: RISC-V SoC, AI accelerator or complete ASIC flow project

Full program syllabus

6–9 months · 500–650+ hours · Theory + Digital Design Lab + HDL Lab + FPGA Lab + Verification Lab + ASIC Flow + Physical Design + Capstone

  • Professional VLSI & Semiconductor Design Program

    6–9 Months | 32 Weeks | 500–650+ Hours — RTL Design • Verification • FPGA • ASIC • Physical Design • DFT • SoC • Semiconductor Engineering. Theory + digital design lab + HDL lab + FPGA lab + verification lab + ASIC flow + physical design + capstone.

    Program objective: Develop industry-ready semiconductor engineers who understand the complete design flow from specification to silicon — not just Verilog syntax in isolation.

    Student journey: Electronics Fundamentals → Digital Logic → Computer Architecture → CMOS & VLSI → Verilog → SystemVerilog → RTL Design → Simulation → Functional Verification → FPGA → Synthesis → STA → Physical Design → DFT → Physical Verification → ASIC/SoC → AI-Assisted EDA → Tape-Out-Oriented Capstone.

    Core promise: Don't just learn Verilog. Learn the complete semiconductor design flow from specification to silicon.

    Target career roles
    • VLSI/RTL/Digital/ASIC/SoC Design Engineer
    • Design Verification, SystemVerilog/UVM Verification Engineer
    • Physical Design, Backend VLSI, P&R, STA Engineer
    • DFT, ATPG, Scan, FPGA Design/Application Engineer
    • Semiconductor R&D, EDA, Hardware/AI Accelerator Engineer
    Three RASA certification levels
    • Level 1 — VLSI Design Professional: Digital logic + CMOS + Verilog + RTL + FPGA
    • Level 2 — Professional ASIC & VLSI Engineer: RTL + SystemVerilog + verification + FPGA + synthesis + STA
    • Level 3 — Advanced Chip Design Engineer: RTL + UVM + physical design + DFT + SoC + AI hardware
    Phase 1 — Electronics & Semiconductor Fundamentals (Weeks 1–2)
    Module 01 — Semiconductor Fundamentals
    • Conductor, insulator, silicon, doping, P/N-type, PN junction
    • Diode, BJT, MOSFET, CMOS; silicon → transistor → logic gate → circuit → IC
    Module 02 — MOSFET Fundamentals
    • NMOS, PMOS, threshold voltage, cutoff/linear/saturation
    • PMOS + NMOS → CMOS logic
    Phase 2 — Digital Logic (Weeks 3–4)
    Module 03 — Digital Logic
    • Binary, decimal, hex, octal; logic gates; Boolean algebra, K-maps
    Module 04 — Combinational Circuits
    • Mux, demux, encoder, decoder, comparator, adder, subtractor, ALU
    • Project: 8-bit ALU
    Module 05 — Sequential Circuits
    • Latch, flip-flop, register, counter, shift register, FSM (Moore/Mealy)
    • Project: traffic-light FSM
    Phase 3 — Computer Architecture (Week 5)
    Module 06 — Digital Computer Architecture
    • CPU, ALU, registers, memory, bus, control unit
    • Instruction, opcode, PC, stack, interrupt; processor + memory + peripherals = system
    Module 07 — Memory Architecture
    • ROM, RAM, SRAM, DRAM, flash; cache, memory hierarchy, memory controller
    Phase 4 — CMOS & VLSI Fundamentals (Weeks 6–7)
    Module 08 — CMOS Digital Design
    • CMOS inverter, noise margin, propagation delay, switching activity
    • Dynamic/static power, leakage; power ↔ performance ↔ area trade-off
    Module 09 — VLSI Design Methodology
    • System, RTL, gate, transistor, layout levels
    • Spec → architecture → RTL → netlist → physical design → layout → manufacturing
    Phase 5 — Verilog HDL (Weeks 8–9)
    Module 10 — Verilog Fundamentals
    • Modules, ports, nets, variables, operators, continuous/procedural blocks
    • always, initial, blocking/non-blocking assignments
    Module 11 — RTL Coding
    • Mux, decoder, counter, register, FIFO, UART, SPI
    • Synthesizable RTL, clocked/combinational logic, reset, enable
    Module 12 — FSM Design
    • Traffic controller, sequence detector, UART/protocol controller
    Phase 6 — SystemVerilog (Weeks 10–11)
    Module 13 — SystemVerilog RTL
    • Logic, arrays, structures, enums, interfaces, packages, assertions
    • Parameterized modules, generate, reusable IP
    Module 14 — SystemVerilog for Verification
    • Classes, objects, randomization, constraints, functional coverage, assertions
    Phase 7 — RTL Design (Weeks 12–14)
    Module 15 — Professional RTL Design
    • Synchronous design, clock domains, reset architecture, pipelining, throughput/latency
    • CDC, synchronizers, handshake, FIFO design
    Module 16 — RTL IP Design
    • UART, SPI, I2C, timer, FIFO, PWM, DMA awareness
    Module 17 — RTL Optimization
    • Area, power, timing; pipelining, resource sharing, logic optimization, clock gating awareness
    Phase 8 — Functional Verification (Weeks 15–17)
    Module 18 — Verification Fundamentals
    • Verification plan, testbench, stimulus, monitor, checker, scoreboard
    • DUT → stimulus → monitor → checker → coverage
    Module 19 — SystemVerilog Verification
    • Directed/random tests, corner cases, error injection
    Module 20 — UVM
    • Test, environment, agent, driver, monitor, sequencer, sequence, scoreboard
    • Project: UVM environment for AXI-lite / UART / SPI IP
    Phase 9 — FPGA (Weeks 18–19)
    Module 21 — FPGA Fundamentals
    • LUT, flip-flop, BRAM, DSP, clock resources, I/O; FPGA vs ASIC trade-offs
    Module 22 — FPGA Development
    • LED, PWM, UART, VGA awareness, motor control, sensor interface
    • Xilinx/AMD, Intel, Lattice FPGA boards
    Phase 10 — Synthesis & STA (Week 20)
    Module 23 — Logic Synthesis
    • RTL → synthesis → gate netlist; constraints, cell libraries, area/timing optimization
    Module 24 — Static Timing Analysis
    • Setup/hold, clock skew, slack, critical path, timing constraints
    • Analyse setup and hold violations
    Phase 11 — Physical Design (Weeks 21–24)
    Module 25 — Physical Design Flow
    • Netlist → floorplan → power planning → placement → CTS → routing → signoff
    Module 26 — Floorplanning
    • Die, core, macro, standard cell, IO, power grid; congestion/timing/power/area
    Module 27 — Placement & CTS
    • Standard cell placement, optimization, congestion; clock buffers, skew, latency
    Module 28 — Routing & Signoff
    • Global/detailed routing, DRC, antenna, signal integrity
    • DRC, LVS, timing signoff, IR drop, electromigration
    Phase 12 — DFT (Week 25)
    Module 30 — Design for Testability
    • Testability, scan chains, scan flip-flops, ATPG, fault models (stuck-at, transition)
    Module 31 — DFT Architecture
    • Scan insertion, test compression, boundary scan, JTAG, BIST
    • Project: scan-based test architecture analysis
    Phase 13 — Physical Verification (Week 26)
    Module 32 — Physical Verification
    • DRC, LVS, ERC, antenna, layout verification
    • Layout → DRC → LVS → signoff flow
    Phase 14 — SoC & Advanced VLSI (Week 27)
    Module 33 — SoC Architecture
    • CPU, GPU/NPU awareness, memory, interconnect, peripherals, security
    • CPU + memory + accelerators + interfaces = SoC
    Module 34 — Bus Protocols
    • AMBA, AXI, AHB, APB; project: AXI-connected peripheral
    Module 35 — Semiconductor IP
    • Reusable/soft/hard IP, verification IP; spec → RTL → verification → synthesis → integration
    Phase 15 — AI & Advanced Chip Design (Week 28)
    Module 36 — AI Hardware
    • Matrix multiplication, MAC units, NN accelerators, tensor processing
    • Parallelism, pipelining, data reuse, memory bandwidth
    • Project: RTL-based neural-network accelerator
    Module 37 — AI for VLSI / EDA
    • RTL optimization, verification, bug detection, test generation, floorplanning, timing/power
    • GenAI for RTL, testbench, debugging, documentation — must simulate, verify and synthesize before trusting
    Phase 16 — Advanced Specializations & Capstone (Weeks 29–32)
    Specialization tracks (post-core)
    • A — RTL Design: SystemVerilog, FSM, pipelining, CDC, low-power; communication IP project
    • B — Verification: Assertions, UVM, constrained random, formal awareness; complete UVM env
    • C — Physical Design: Floorplan → placement → CTS → routing → STA → DRC/LVS signoff
    • D — DFT: Scan, ATPG, compression, JTAG, BIST
    • E — FPGA: Constraints, timing, interfaces, hardware acceleration
    • F — SoC: CPU, AMBA, AXI, memory, peripherals, mini SoC
    • G — AI Chip: NN architecture, MAC arrays, CNN/matrix accelerator RTL
    • H — Automotive VLSI: Automotive SoC, MCU, CAN, safety, control IP (links to EV program)
    RASA Chip Design Challenge — capstone options
    • Option 1 — 32-bit Mini Processor: ALU, registers, control, memory, UART → spec → RTL → verification → synthesis → FPGA
    • Option 2 — RISC-V SoC: CPU + RAM + UART + GPIO + timer → RTL → verification → FPGA
    • Option 3 — AI Accelerator: input → buffer → MAC array → accumulator → output; throughput/latency/area/power
    • Option 4 — Complete ASIC Flow (advanced): RTL → verification → synthesis → STA → floorplan → P&R → DRC/LVS → signoff
    • Option 5 — VLSI Verification: verification plan, SV testbench, assertions, coverage, UVM, bug report
    Labs, toolkit, portfolio & assessment
    Seven dedicated labs
    • Digital Design, HDL, FPGA, Verification, ASIC Design, Physical Design, Chip Design (RTL → GDS-oriented flow)
    EDA toolkit
    • Verilog/SystemVerilog, Questa/VCS/Xcelium awareness, Vivado/Quartus, UVM
    • Design Compiler/Genus, PrimeTime/Tempus, Innovus/ICC2, Tessent, OpenROAD, Python/Tcl, Git
    10–12+ project portfolio
    • Digital: ALU, FSM, FIFO, UART, SPI
    • RTL: UART/PWM/memory controllers; FPGA digital system; SV testbench, UVM project
    • Advanced: AXI peripheral, RISC-V mini SoC, AI accelerator, complete ASIC physical-design flow
    Assessment framework
    • Semiconductor (5%), digital design (10%), CMOS/VLSI (5%), Verilog (10%), SystemVerilog (5%), RTL (10%), verification (10%), UVM (5%), FPGA (5%), synthesis/STA (5%), physical design (10%), DFT (5%), SoC (5%), AI hardware (5%), capstone (10%)

    Six engineering layers: DEVICE (semiconductor + MOSFET + CMOS) → DIGITAL (logic + FSM + architecture) → RTL (Verilog + SystemVerilog + IP) → VERIFICATION (simulation + assertions + UVM + coverage) → SILICON (synthesis + STA + physical design + DFT + signoff) → INTELLIGENCE (SoC + AI accelerators + HW/SW co-design).

    Cross-program links: PLC & Embedded Systems · EV Engineering · Drone Engineering · Medical Robotics · Industrial Automation · AI & Robotics

    Enquire about this program

Common questions

  • Is this only a Verilog programming course?

    No. Verilog is one component. The program covers the full stack — CMOS, RTL, UVM verification, FPGA, synthesis, STA, physical design, DFT, SoC and AI hardware — aligned with how chips are actually designed in the semiconductor industry.

  • Which EDA tools does RIA use?

    Hands-on work uses industry-standard and educational tools — Verilog/SystemVerilog simulators, Vivado/Quartus for FPGA, UVM for verification, plus synthesis/STA/physical-design awareness with Design Compiler, PrimeTime, Innovus and OpenROAD where licensing permits. Exact commercial stack depends on RIA's academic partnerships.

  • How does VLSI connect to EV and embedded at RIA?

    VLSI feeds directly into RIA's hardware ecosystem — Automotive VLSI specialization links to EV Engineering (BMS/VCU SoC), PLC & Embedded (industrial controllers/FPGA), and AI & Robotics (edge AI accelerators for drones and medical devices).

Skills you build

  • End-to-end chip design from specification through RTL, verification and FPGA
  • Professional UVM verification environments with coverage-driven methodology
  • Synthesis, STA and physical-design signoff awareness
  • SoC integration with AXI/AMBA and semiconductor IP development
  • Professional VLSI document library (spec, verification plan, synthesis/STA reports, DRC/LVS)

Who this is for

  • ECE/EEE and electronics engineering students and graduates
  • Embedded engineers moving into RTL, FPGA or ASIC design
  • Software engineers transitioning to hardware verification (UVM)
  • Learners targeting RTL, verification, physical design, DFT or AI chip roles

Enquire about VLSI & Semiconductor Design

Explore other School of Robotics programmes

PLC & Embedded Systems
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